The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

Jan. 09, 2024
Applicant:

Efficient Power Conversion Corporation, El Segundo, CA (US);

Inventors:

Jianjun Cao, Torrance, CA (US);

Wen-Chia Liao, Torrance, CA (US);

Muskan Sharma, Torrance, CA (US);

Robert Strittmatter, Tujunga, CA (US);

Alexander Lidow, Topanga, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/00 (2025.01); H10D 30/47 (2025.01); H10D 62/10 (2025.01); H10D 62/85 (2025.01); H10D 64/62 (2025.01);
U.S. Cl.
CPC ...
H10D 64/112 (2025.01); H10D 30/47 (2025.01); H10D 62/102 (2025.01); H10D 62/85 (2025.01); H10D 64/62 (2025.01);
Abstract

An enhancement mode GaN transistor that includes a multi-region field plate which partially overlaps the gate and partially overlaps a barrier offset layer. The multi-region field plate includes a section of increased height with respect to the channel layer over the portion of the gate nearest the drain contact, and a section of reduced height with respect to the channel layer over the edge or transition of the barrier offset layer, minimizing the peak electric field at the corner of the gate and at the edge or transition of the barrier offset layer.


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