The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

Sep. 07, 2023
Applicants:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Toshiba Electronic Devices & Storage Corporation, Tokyo, JP;

Inventors:

Katsuhisa Tanaka, Himeji Hyogo, JP;

Hiroshi Kono, Himeji Hyogo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/66 (2025.01); H10D 62/10 (2025.01); H10D 62/832 (2025.01); H10D 64/00 (2025.01);
U.S. Cl.
CPC ...
H10D 30/665 (2025.01); H10D 30/668 (2025.01); H10D 62/111 (2025.01); H10D 64/111 (2025.01); H10D 62/8325 (2025.01);
Abstract

According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the second conductivity type, a sixth semiconductor region of the second conductivity type, a seventh semiconductor region of the second conductivity type, an eighth semiconductor region of the second conductivity type, a second electrode, and a third electrode. The fourth semiconductor region is located around the second semiconductor region and the gate electrode. The fourth, fifth and sixth semiconductor regions are separated from each other. The fourth, seventh and eighth semiconductor regions are separated from each other. The third electrode is located on the eighth semiconductor region with an insulating layer interposed.


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