The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2026
Filed:
Aug. 17, 2023
Nxp Usa, Inc., Austin, TX (US);
Philippe Renaud, Chandler, AZ (US);
Congyong Zhu, Gilbert, AZ (US);
NXP USA, INC., Austin, TX (US);
Abstract
An embodiment of a semiconductor device includes a semiconductor substrate and one or more lower dielectric layers on the surface of the substrate. Source, drain, gate, and field plate openings, which are formed in a self-aligned manner, extend through the lower dielectric layer(s) to the substrate. A conformal dielectric layer is disposed over the lower dielectric layer(s) and into the gate and field plate openings. The conformal dielectric layer includes first portions on sidewalls of the gate opening, second portions on sidewalls of the field plate opening, and a third portion on the substrate at a bottom extent of the field plate opening. Gate spacers are formed on the first portions of the conformal dielectric layer. A gate electrode in the gate opening contacts the gate spacers and the semiconductor substrate. A field plate in the field plate opening contacts the second and third portions of the conformal dielectric layer.