The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

Mar. 09, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yi-Hsuan Chen, Taoyuan City, TW;

Kuen-Yi Chen, Hsinchu City, TW;

Yi Ching Ong, Hsinchu, TW;

Yu-Wei Ting, Taipei City, TW;

Kuo-Chi Tu, Hsin-Chu, TW;

Kuo-Ching Huang, Hsinchu City, TW;

Harry-Hak-Lay Chuang, Zhubei city, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/20 (2023.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01); H10D 64/68 (2025.01); H10W 20/41 (2026.01); H10W 20/42 (2026.01);
U.S. Cl.
CPC ...
H10B 51/20 (2023.02); H10D 30/0415 (2025.01); H10D 30/701 (2025.01); H10D 64/033 (2025.01); H10D 64/689 (2025.01); H10W 20/42 (2026.01); H10W 20/435 (2026.01);
Abstract

A method of forming a memory device according to the present disclosure includes forming a trench in a first substrate of a first wafer, depositing a data-storage element in the trench, performing a thermal treatment to the first wafer to improve a crystallization in the data-storage element, forming a first redistribution layer over the first substrate, forming a transistor in a second substrate of a second wafer, forming a second redistribution layer over the second substrate, and bonding the first wafer with the second wafer after the performing of the thermal treatment. The data-storage element is electrically coupled to the transistor through the first and second redistribution layers.


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