The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12696445 B1

Date of Patent:

Jul. 28, 2026

Filed:

Nov. 28, 2023

Integrated circuit with back-side metal line, method of fabricating the same, and layout method

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chien-Ying Chen, Hsinchu, TW;

Yao-Jen Yang, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

Hauptman Ham, LLP

Primary Examiner:

Allison Bernstein

Int. Cl.

CPC ...

H10B 20/25 (2023.01); G06F 30/392 (2020.01);

U.S. Cl.

CPC ...

H10B 20/25 (2023.02); G06F 30/392 (2020.01);

Abstract

A method of generating an integrated circuit (IC) layout diagram includes overlapping an active region with a plurality of gate regions, thereby defining a program transistor and a read transistor of a one-time-programmable (OTP) bit, overlapping a through via region with a gate region of the plurality of gate regions or with the active region, and overlapping the through via region with a metal region of a back-side metal layer.

Find Patent Forward Citations

Quick Actions:

Chen, Chien-Ying. (2026). Integrated circuit with back-side metal line, method of fabricating the same, and layout method (U.S. Patent No. 12696445). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12696445

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile