The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2026
Filed:
Sep. 03, 2024
Nxp Usa, Inc., Austin, TX (US);
Prakhar Tandon, Hyderabad, IN;
Shivesh Kumar Dubey, Hyderabad, IN;
Uma Maheswara Reddy Poreddy, Hyderabad, IN;
NXP USA, Inc., Austin, TX (US);
Abstract
A delay locked loop circuit comprising: a voltage-controlled delay line (VCDL); a phase detector circuit that is configured to process a first and a last output signal of the VCDL in order to provide: i) an up-pulse signal; and ii) a down-phase signal; a charge pump that is configured to provide a feedback voltage signal based on the up-pulse signal and the down-pulse signal; a phase signal processor that is configured to process the up-pulse signal and the down-pulse signal in order to provide a delay code locking signal, which is representative of whether or not the first output signal is 2Π radians out of phase with the last output signal; a delay code setter that is configured to provide a delay code setting signal that represents one of a sequence of different candidate delay codes. The delay locked loop circuit may operate in calibration and active modes.