Layout method and semiconductor structure for ic

Abstract

A layout method is provided. A timing analysis is performed based on design data of a standard cell to classify a plurality of device units of the standard cell into a timing-critical group and a non-timing-critical group. A plurality of first sources regions in the device units of the non-timing-critical group are aligned with a plurality of second sources regions in the device units of the timing-critical group in a first direction in floorplan of the standard cell in a layout. The device units of the timing-critical group are arranged in a first row of a cell array and the device units of the non-timing-critical group are arranged in a second row of the cell array. The first and second rows of the cell array share a common power line. First active regions of the first row are wider than second active regions of the second row.