The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

May. 01, 2023
Applicant:

Synopsys, Inc., Sunnyvale, CA (US);

Inventors:

Kranthi Kandula, Telangana, IN;

Ramalingam Kolisetti, Andhra Pradesh, IN;

Firooz Massoudi, Palo Alto, CA (US);

Anubhav Sinha, Telangana, IN;

Sadashiv Chimmad, Karnataka, IN;

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/3183 (2006.01); G01R 31/317 (2006.01); G01R 31/3185 (2006.01); G06F 30/3312 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3312 (2020.01); G01R 31/31723 (2013.01); G01R 31/318307 (2013.01); G01R 31/318536 (2013.01);
Abstract

A method includes determining a plurality of threshold margins corresponding to a plurality of functional paths in an electronic circuit. The method further includes storing the plurality of threshold margins corresponding to the plurality of functional paths in a memory. The method further includes receiving a first trigger from a processing device. The method further includes responsive to receiving the first trigger, monitoring at least one of the plurality of threshold margins corresponding to at least one of the plurality of functional paths in view of a previously determined threshold margin stored in the memory and corresponding to the at least one of the plurality functional paths.


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