The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2026

Filed:

Mar. 17, 2023
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Pei Luan Pok, Melaka, MY;

Swee Kah Lee, Melaka, MY;

Soon Lock Goh, Malacca, MY;

Chee Hong Lee, Paya Rumput, MY;

Samsun Paing, Tangkak, MY;

Chee Chiew Chong, Batu Caves, MY;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 74/01 (2026.01); H10W 70/04 (2026.01); H10W 72/00 (2026.01);
U.S. Cl.
CPC ...
H10W 74/019 (2026.01); H10W 70/04 (2026.01); H10W 74/014 (2026.01); H10W 72/012 (2026.01); H10W 72/0198 (2026.01);
Abstract

A method of forming a semiconductor package includes providing a baseplate, mounting a semiconductor die on the baseplate with a main surface of the semiconductor die facing away from the baseplate, forming vertical interconnect elements on the main surface of the semiconductor die, forming an encapsulant on the baseplate that encapsulates the semiconductor die, exposing the vertical interconnect elements at an upper surface of the encapsulant, forming a first level metal pad on the upper surface of the encapsulant that contacts the exposed vertical interconnect elements, and forming structured metal regions on the upper surface of the encapsulant, wherein forming the structured metal regions includes structuring the first level metal pad.


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