The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 2026
Filed:
Nov. 15, 2023
Renesas Electronics Corporation, Tokyo, JP;
Hiroshi Yanagigawa, Tokyo, JP;
Hideki Niwayama, Tokyo, JP;
Hiroyoshi Kudou, Tokyo, JP;
Kazuhisa Mori, Tokyo, JP;
Kodai Wada, Tokyo, JP;
Renesas Electronics Corporation, Tokyo, JP;
Abstract
In a semiconductor substrate SUB, a trench TR is formed. A gate-electrode GEis formed inside the trench TR via a gate insulating film GI. A body region PB, a well region PWand a well region NWare formed. A source-region NS is formed in the body-region PB. In the well region PW, an n-type source region and an n-type drain region are formed. In the well region NW, a p-type source region and a p-type drain region are formed. An interlayer insulating film ILis formed on the upper surface of semiconductor substrate SUB. In the interlayer insulating film IL, a hole CHis formed in the source region NS and in the body region PB. Holes CHare formed in the interlayer insulating film ILso as to reach the n-type source region, the n-type drain region, the p-type source region and the p-type drain region.