The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2026

Filed:

Dec. 07, 2023
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Bogdan Cezar Zota, Rüschlikon, CH;

Lorenzo Rocchino, Zurich, CH;

Federico Balduini, Switzerland, CH;

Heinz Schmid, Waedenswil, CH;

Bernd W. Gotsmann, Horgen, CH;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/13 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10D 62/151 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01);
Abstract

A semiconductor structure includes a nanosheet stack on a substrate. The nanosheet stack has alternating layers of channel nanosheets and sacrificial nanosheets, which are formed between a first source/drain (S/D) region and a second S/D region. The semiconductor structure further includes a gate structure on the nanosheet stack, and a three-dimensional (3D) Dirac energy filter. The three-dimensional (3D) Dirac energy filter is formed on a portion of the substrate located in the first S/D region and includes a portion that contacts the nanosheet stack. A first S/D is on the 3D Dirac energy filter in the first S/D region, and a second S/D is on the substrate of the second S/D region.


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