The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2026

Filed:

Jul. 11, 2024
Applicant:

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Francesco Tomaiuolo, Acireale, IT;

Marco Ruta, San Gregorio di Catania, IT;

Michelangelo Pisasale, Catania, IT;

Marion Helne Grimal, Catania, IT;

Luigi Buono, Gravina di Catania, IT;

Antonino Conte, Tremestieri Etneo, IT;

Diego De Costantini, Augusta, IT;

Marco Eugenio Gibilaro, Aci Castello, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0064 (2013.01); G11C 13/0004 (2013.01); G11C 13/0069 (2013.01);
Abstract

A Phase Change Memory (PCM) device includes sets of cells in which a binary logic level is written by a write operation. Each cell is included in a respective set of cells in the sets of cells. The write operation includes: performing write verify operations on the cells to identify an actual logic level stored in the cells; checking if the identified actual logic level matches a certain the binary logic level; in response to the checking determining that in at least one cell the actual logic level fails to match the binary logic level, correcting the actual logic level to match the binary logic level by performing: a set write operation in case the binary logic level is a high logic level, or a reset write operation in case the binary logic level is a low logic level.


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