The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Jun. 27, 2024
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Owen R. Fay, Meridian, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H10P 72/70 (2026.01); H10W 20/42 (2026.01); H10W 20/43 (2026.01); H10W 20/44 (2026.01); H10W 70/65 (2026.01); H10W 72/00 (2026.01); H10W 72/90 (2026.01); H10W 90/00 (2026.01); H10W 72/20 (2026.01); H10W 90/20 (2026.01); H10W 90/26 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10P 72/74 (2026.01); H10W 20/42 (2026.01); H10W 20/43 (2026.01); H10W 20/4405 (2026.01); H10W 20/4421 (2026.01); H10W 70/65 (2026.01); H10W 72/072 (2026.01); H10W 72/90 (2026.01); H10P 72/743 (2026.01); H10W 72/01235 (2026.01); H10W 72/01255 (2026.01); H10W 72/07254 (2026.01); H10W 72/242 (2026.01); H10W 72/247 (2026.01); H10W 72/252 (2026.01); H10W 90/26 (2026.01); H10W 90/291 (2026.01); H10W 90/297 (2026.01); H10W 90/722 (2026.01);
Abstract

Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.


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