The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Apr. 17, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seokgeun Ahn, Suwon-si, KR;

Seokhyun Lee, Suwon-si, KR;

Hwanyoung Choi, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H10W 20/42 (2026.01); H10W 70/65 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 74/15 (2026.01); H10W 90/00 (2026.01); H10W 72/90 (2026.01); H10W 74/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 74/129 (2026.01); H10W 20/42 (2026.01); H10W 70/65 (2026.01); H10W 74/012 (2026.01); H10W 74/15 (2026.01); H10W 90/00 (2026.01); H10W 72/9226 (2026.01); H10W 72/923 (2026.01); H10W 72/9413 (2026.01); H10W 74/00 (2026.01); H10W 90/297 (2026.01); H10W 90/724 (2026.01);
Abstract

A semiconductor package includes: a substrate; a circuit layer disposed on a lower surface of the substrate, the circuit layer including an interconnection structure; a first redistribution structure disposed adjacent to the circuit layer, the first redistribution structure including a first redistribution layer; a connection structure including a first connection via electrically connected to the first redistribution layer, a second connection via electrically connected to the interconnection structure, and a connection interconnection interconnecting the first and second connection vias; a semiconductor chip disposed below the first redistribution structure, and electrically connected to the first redistribution layer; a first vertical connection structure disposed on a lower surface of the circuit layer; a second vertical connection structure disposed on a lower surface of the connection structure; and a second redistribution structure disposed below the semiconductor chip and the first and second vertical connection structures.


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