The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Nov. 27, 2023
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Scott R. Cyr, Boise, ID (US);

David P. Gooch, Meridian, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 11/408 (2006.01); H10B 80/00 (2023.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 72/30 (2026.01); H10W 72/50 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); G11C 11/408 (2013.01); H10B 80/00 (2023.02); H10W 70/611 (2026.01); H10W 70/685 (2026.01); H10W 90/00 (2026.01); H10W 72/07354 (2026.01); H10W 72/347 (2026.01); H10W 72/552 (2026.01); H10W 72/5522 (2026.01); H10W 72/5524 (2026.01); H10W 72/5525 (2026.01); H10W 72/865 (2026.01); H10W 72/884 (2026.01); H10W 90/732 (2026.01); H10W 90/734 (2026.01); H10W 90/752 (2026.01); H10W 90/754 (2026.01);
Abstract

Methods, systems, and devices for chip select wiring for a dual device package are described. A circuit board includes a plurality of layers, the plurality of layers including a first outer layer, a second inner layer, and a third outer layer. The circuit board also includes first and second chip select (CS) signal lines routed through the second inner layer of the circuit board, first and second memory devices coupled with the first outer layer and the third outer layer, respectively, a first via coupling the first CS signal line with a first upper memory die of the first memory device and a second lower memory die of the second memory device, and a second via coupling the second CS signal line with a second upper memory die of the second memory device and a first lower memory die of the first memory device.


Find Patent Forward Citations

Cyr, Scott. (2026). Chip select wiring for a dual device package (U.S. Patent No. 12685197). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12685197

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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