The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Sep. 21, 2023
Applicant:

Toppan Inc., Tokyo, JP;

Inventors:

Yuki Umemura, Tokyo, JP;

Takehisa Takada, Tokyo, JP;

Tomoyuki Ishii, Tokyo, JP;

Assignee:

TOPPAN INC., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/05 (2026.01); H05K 1/02 (2006.01); H05K 1/03 (2006.01); H05K 1/11 (2006.01); H05K 1/181 (2026.01); H05K 3/00 (2006.01); H05K 3/40 (2006.01); H10D 1/68 (2025.01); H10W 46/00 (2026.01); H10W 70/63 (2026.01); H10W 70/685 (2026.01);
U.S. Cl.
CPC ...
H10W 70/095 (2026.01); H05K 1/0266 (2013.01); H05K 1/0306 (2013.01); H05K 1/115 (2013.01); H05K 1/181 (2013.01); H05K 3/0026 (2013.01); H05K 3/4038 (2013.01); H10D 1/68 (2025.01); H10W 46/00 (2026.01); H10W 70/635 (2026.01); H10W 70/685 (2026.01); H05K 2203/107 (2013.01); H10W 46/301 (2026.01);
Abstract

A method for manufacturing a wiring board, including a step A of forming a laser-modified portion in a glass substrate by applying laser light to the glass substrate from a first surface to an opposite surface of the glass substrate; a step B of forming a first surface wiring layer including a MIM capacitor on the first surface of the glass substrate; a step C of performing an etching process on a surface of the glass substrate opposite to the first surface to form a through via in the laser-modified portion and form a second surface of the glass substrate opposite to the first surface; and a step D of forming a through electrode in the through via and forming, on the second surface, a second surface wiring layer that is connected to the first surface wiring layer via the through electrode.


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