The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 2026
Filed:
Sep. 27, 2023
Nxp Usa, Inc., Austin, TX (US);
Douglas Michael Reber, Austin, TX (US);
Ertugrul Demircan, Eugene, OR (US);
Mehul D. Shroff, Austin, TX (US);
NXP USA, Inc., Austin, TX (US);
Abstract
An integrated circuit includes a dielectric layer located over one or more metal interconnect layers. The dielectric layer includes selective regions of implanted stress-setting dopants to provide different stress profiles in the dielectric layer to counteract the stress imparted from package structures. Accordingly, the effect of the stress imparted by package structures in a substrate can be negated by the placement of stress-setting dopants in selective areas of the dielectric layer.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile