The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Aug. 23, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jonggyu Lee, Suwon-si, KR;

Jaechoon Kim, Suwon-si, KR;

Taehwan Kim, Suwon-si, KR;

Hwanjoo Park, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 40/10 (2026.01); H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 72/30 (2026.01); H10W 74/15 (2026.01); H10W 76/60 (2026.01); H10W 76/63 (2026.01); H10W 76/67 (2026.01);
U.S. Cl.
CPC ...
H10W 40/10 (2026.01); H10W 90/00 (2026.01); H10W 72/07351 (2026.01); H10W 72/07355 (2026.01); H10W 72/357 (2026.01); H10W 72/365 (2026.01); H10W 72/367 (2026.01); H10W 72/877 (2026.01); H10W 74/15 (2026.01); H10W 76/60 (2026.01); H10W 76/63 (2026.01); H10W 76/67 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01); H10W 90/736 (2026.01);
Abstract

A semiconductor package includes a package substrate, a semiconductor chip on the package substrate and having a first surface facing the package substrate and a second surface, opposite to the first surface, an encapsulant disposed on the package substrate and on a side surface of the semiconductor chip, a heat dissipation member on the semiconductor chip and spaced apart from the semiconductor chip, a bonding enhancing layer on the second surface of the semiconductor chip, a thermal interface material layer on the bonding enhancing layer and in a gap between the bonding enhancing layer and the heat dissipation member, wherein the thermal interface material layer includes liquid metal, and a porous barrier structure formed of a metal material and surrounding the bonding enhancing layer and the thermal interface material layer.


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