The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

May. 24, 2024
Applicant:

Invention and Collaboration Laboratory, Inc., Taipei City, TW;

Inventors:

Chun Shiah, Hsinchu City, TW;

Shih-Hsing Wang, Hsinchu, TW;

Chao-Chun Lu, Taipei City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 5/06 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01); G11C 11/4097 (2006.01); H10B 12/00 (2023.01); H10W 10/00 (2026.01); H10W 10/17 (2026.01); H10W 20/00 (2026.01); H10W 20/20 (2026.01);
U.S. Cl.
CPC ...
H10W 20/20 (2026.01); G11C 5/063 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); G11C 11/4097 (2013.01); H10B 12/09 (2023.02); H10B 12/482 (2023.02); H10B 12/50 (2023.02); H10W 10/014 (2026.01); H10W 10/17 (2026.01); H10W 20/023 (2026.01); H10W 20/069 (2026.01);
Abstract

A memory array circuit includes a semiconductor substrate, a bitline, a complementary bitline, and a bitline sense amplifier circuit, wherein the bitline sense amplifier circuit includes a first plurality of transistors and a first set of connection lines. The semiconductor substrate has an original surface. The bitline sense amplifier circuit is connected to the bitline and the complementary bitline. Each transistor includes a gate node, a first conductive node, and a second conductive node. The first set of connection lines connects the first conductive nodes of the first plurality of transistors to the bitline and the complementary bitline. The first set of connection lines are under the original surface of the semiconductor substrate.


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