The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Dec. 22, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Oscar Van Der Straten, Guilderland Center, NY (US);

Scott A. Devries, Albany, NY (US);

Koichi Motoyama, Clifton Park, NY (US);

Chih-Chao Yang, Glenmont, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/00 (2026.01); H10P 50/00 (2026.01); H10W 20/41 (2026.01);
U.S. Cl.
CPC ...
H10W 20/057 (2026.01); H10P 50/73 (2026.01); H10W 20/033 (2026.01); H10W 20/076 (2026.01); H10W 20/425 (2026.01); H10W 20/435 (2026.01);
Abstract

A chip is manufactured using a method for forming a back-end-of-line (BEOL) layer on an IC chip surface comprises providing a first layer on top of a substrate layer of the IC chip, the first layer comprising a bottom portion of a metallic fill region having a first width as seen in a vertical cross-section of the IC chip. The method further provides a second layer on top of the first layer. The second layer comprises a middle portion of the metallic fill region having a second width that is wider than the bottom portion of the metallic fill region. The method provides a third layer on top of the second layer. The third layer comprises a top portion of the metallic fill region having a third width as seen in the vertical cross-section of the IC chip that is narrower than the middle portion of the metallic fill region.


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