The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Aug. 25, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yen-Chih Huang, Hsinchu, TW;

Li-An Sun, Hsinchu, TW;

Chih-Hao Chen, Hsinchu, TW;

Chung-Chuan Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/00 (2026.01);
U.S. Cl.
CPC ...
H10W 20/056 (2026.01); H10W 20/074 (2026.01); H10W 20/075 (2026.01); H10W 20/076 (2026.01); H10W 20/096 (2026.01); H10W 20/033 (2026.01);
Abstract

A semiconductor device includes a FEOL structure and a BEOL structure. The BEOL structure is formed over the FEOL structure and includes a conductive layer, an etching stop layer (ESL) structure, a through via and a barrier layer. The ESL structure is formed over the conductive layer and has a first recess and a lateral surface. The through via passes through the ESL structure to form the first recess and the lateral surface. The barrier layer covers the lateral surface and the first recess. The first recess is recessed with respect to the lateral surface, and the first recess has a first depth ranging between 1 nm and 7 nm.


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