The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Oct. 05, 2023
Applicant:

United Microelectronics Corp., Hsin-Chu City, TW;

Inventors:

Chih-Wei Kuo, Tainan City, TW;

Chung-Yi Chiu, Tainan City, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Hsin-Chu City, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10N 50/01 (2023.01); H10B 61/00 (2023.01); H10N 50/80 (2023.01);
U.S. Cl.
CPC ...
H10N 50/01 (2023.02); H10B 61/00 (2023.02); H10N 50/80 (2023.02);
Abstract

A manufacturing method of a memory device includes following steps. Memory units are formed on a substrate. Each memory unit includes a first electrode, a second electrode disposed above the first electrode in a vertical direction, and a memory material layer disposed between the first electrode and the second electrode. A conformal spacer layer is formed on the memory units. A non-conformal spacer layer is formed on the conformal spacer layer. A first opening is formed penetrating through a first portion of the non-conformal spacer layer between the memory units in a horizontal direction and a first portion of the conformal spacer layer on the first portion of the conformal spacer layer in the vertical direction. A thickness of a second portion of the non-conformal spacer layer on the second electrode is greater than a thickness of the second portion of the non-conformal spacer layer on the memory material layer.


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