The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 2026
Filed:
Sep. 13, 2023
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventors:
Bong Seok Jeon, Gyeonggi-do, KR;
Ji Yong Kim, Gyeonggi-do, KR;
Hai Won Kim, Gyeonggi-do, KR;
Jeong Hyun Lee, Gyeonggi-do, KR;
Assignee:
SK hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H10B 12/00 (2023.01); H10D 84/01 (2026.01); H10D 84/83 (2025.01); H10W 10/00 (2026.01); H10W 10/17 (2026.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H10B 12/033 (2023.02); H10B 12/0335 (2023.02); H10B 12/05 (2023.02); H10B 12/053 (2023.02); H10B 12/482 (2023.02); H10D 84/0149 (2025.01); H10D 84/0151 (2025.01); H10D 84/83 (2025.01); H10W 10/014 (2026.01); H10W 10/17 (2026.01);
Abstract
A method for forming a semiconductor device may include forming, on a substrate, a trench which delimits a preliminary active region. A buffer layer may be formed on the preliminary active region using a first heat treatment process that is performed at 520° C. to 580° C. A sacrificial layer may be formed by replacing the buffer layer. An active region may be exposed by removing the sacrificial layer. A semiconductor liner may be formed on the active region.