The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Oct. 15, 2024
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Uppili S. Raghunathan, Essex Junction, VT (US);

Aaron L. Vallett, Jericho, VT (US);

Venkata Narayana Rao Vanukuru, Bangalore, IN;

Steven M. Shank, Jericho, VT (US);

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/13 (2025.01); H10D 64/23 (2025.01); H10D 84/40 (2025.01);
U.S. Cl.
CPC ...
H10D 62/137 (2025.01); H10D 64/231 (2025.01); H10D 84/401 (2025.01);
Abstract

The disclosure provides structures and related methods to provide a source/drain (S/D) terminal within a subcollector. A structure according to the disclosure includes a field effect transistor (FET) structure having a source/drain (S/D) terminal within a semiconductor layer, and a gate structure on the semiconductor layer. A bipolar transistor (BT) structure is on the FET structure and includes a subcollector within the semiconductor layer, and a collector-base-emitter stack on the subcollector and above the semiconductor layer.


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