The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Jun. 14, 2024
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Witold Kula, Gilroy, CA (US);

Gurtej S. Sandhu, Boise, ID (US);

John A. Smythe, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10B 12/00 (2023.01); H10D 62/80 (2025.01); H10P 14/20 (2026.01); H10P 14/692 (2026.01); H10P 14/24 (2026.01);
U.S. Cl.
CPC ...
H10D 30/6728 (2025.01); H10B 12/30 (2023.02); H10D 30/6733 (2025.01); H10D 30/6757 (2025.01); H10D 62/80 (2025.01); H10D 62/882 (2025.01); H10P 14/3238 (2026.01); H10P 14/3436 (2026.01); H10P 14/69391 (2026.01); H10P 14/24 (2026.01);
Abstract

An apparatus including an array of memory cells comprising transistors is disclosed. One or more of the transistors comprise a crystalline material extending substantially transverse to a base material. A gate dielectric material is adjacent to the crystalline material. A two-dimensional material of a channel region directly intervenes between the gate dielectric material and the crystalline material. The gate dielectric material overlies additional portions of the two-dimensional material of the channel region. One or more gates are adjacent to the gate dielectric material. An electronic device is also disclosed comprising one or more of the transistors. The one or more of the transistors comprise a channel region, a gate dielectric region adjacent to the channel region, and one or more gates adjacent to the gate dielectric region. The channel region comprises opposing sidewalls separated by a pillar structure and substantially perpendicular to a base material.


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