The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Jul. 14, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Jui-Che Tsai, Hsinchu, TW;

Chia-En Huang, Hsinchu, TW;

Tung-Cheng Chang, Hsinchu, TW;

Chun-Ying Lee, Hsinchu, TW;

Yih Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 29/12 (2006.01); G11C 29/46 (2006.01);
U.S. Cl.
CPC ...
G11C 29/12015 (2013.01); G11C 29/1201 (2013.01); G11C 29/46 (2013.01);
Abstract

A circuit includes one or more functional circuits, and a clock generation circuit operatively coupled to the one or more functional circuits. The clock generation circuit is configured to: receive a control signal to switch the one or more functional circuits between a first operation mode and a second operation mode; receive a first clock signal and a second clock signal corresponding to the first operation mode and the second operation mode, respectively; and output, to the one or more functional circuits, a clock pulse signal based on either the first clock signal or the second clock signal. The clock generation circuit is configured to generate either a first conduction path to output the clock pulse signal or a second conduction path to output the clock pulse signal. Each of the first and second conduction paths includes a predefined number of gate delays.


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