The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Jun. 04, 2024
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Edric Goh, Singapore, SG;

Dheeraj Srinivasan, San Jose, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/3404 (2013.01); G11C 2207/2254 (2013.01);
Abstract

A memory device can include a memory array including a plurality of memory cells coupled to a control logic. The control logic is to initiate a program operation on one or more memory cells of a first segment of the memory array, wherein the program operation comprises a first calibration phase. The control logic can also read a first stored value corresponding to a first voltage applied during a second calibration phase for a second segment of the memory array, the second calibration phase before the first calibration phase. The control logic can further read a second stored value corresponding to an offset value associated with the first voltage. Additionally, the control logic can determine a second voltage for application during the calibration phase responsive to reading the first stored value and the second stored value.


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