The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Jul. 29, 2024
Applicant:

Synopsys, Inc., Sunnyvale, CA (US);

Inventors:

Kailash Kumar, Noida, IN;

Prateek Singh, Noida, IN;

Manoj Kumar, Greater Noida, IN;

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/10 (2006.01); H03K 3/037 (2006.01); H03K 5/24 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G06F 13/10 (2013.01); H03K 3/037 (2013.01); H03K 5/24 (2013.01); H03K 19/20 (2013.01); G06F 2213/40 (2013.01);
Abstract

Systems and methods for load compensation are presented to support a wide range of capacitive loads on a pad coupled to an I/O transmitter. The I/O transmitter includes I/O architecture coupled to a pad and a calibration circuit coupled to the I/O architecture. The calibration circuit includes sensing circuitry, pulse generation circuitry coupled to the sensing circuitry and control bit generation circuitry coupled to the pulse generation circuitry. The control bit generation circuitry generates control bits proportional to load variations detected at the pad and feeds the control bits to the I/O architecture to modulate rise and fall times of pulsed signals at the pad.


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