The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Dec. 15, 2022
Applicant:

Murata Manufacturing Co., Ltd., Nagaokakyo, JP;

Inventors:

Altti Torkkeli, Tuusula, FI;

Hidetoshi Fujii, Espoo, FI;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B81C 1/00 (2006.01); B81B 3/00 (2006.01);
U.S. Cl.
CPC ...
B81C 1/00968 (2013.01); B81B 3/001 (2013.01); B81C 2201/0133 (2013.01); B81C 2201/0178 (2013.01);
Abstract

A method for manufacturing a structural layer in a silicon wafer is provide. The silicon wafer has at least two areas vertically recessed to at least two recess depths, with the first recess depth being greater than the second recess depth. The method includes forming a silicon dioxide pattern, a mask layer and a silicon dioxide pad layer, etching the structural layer in a main LOCOS oxidation process, and removing the formed layers exposing the recessed structural layer. The manufactured structural layer has a bump structure with the recess depth smaller than the second recess depth, and the recessed area has no edge steps.


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