The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Jul. 25, 2023
Applicant:

Sandisk Technologies, Inc., Milpitas, CA (US);

Inventor:

Hiroki Yabe, Yokohama, JP;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/685 (2026.01); G11C 7/18 (2006.01); G11C 16/28 (2006.01); H10B 43/35 (2023.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/90 (2026.01); H10W 74/10 (2026.01); H10W 80/00 (2026.01); H10W 90/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 70/685 (2026.01); G11C 7/18 (2013.01); G11C 16/28 (2013.01); H10B 43/35 (2023.02); H10W 90/00 (2026.01); H10W 90/701 (2026.01); H10W 72/07253 (2026.01); H10W 72/232 (2026.01); H10W 72/932 (2026.01); H10W 74/10 (2026.01); H10W 80/732 (2026.01); H10W 90/297 (2026.01); H10W 90/722 (2026.01); H10W 90/732 (2026.01); H10W 90/792 (2026.01);
Abstract

Technology is disclosed herein for a memory device with multiple dies bonded together. The memory device may be referred to herein as an integrated memory assembly. The integrated memory assembly has a control semiconductor die and two or more memory semiconductor dies. In one embodiment, each memory semiconductor die has a memory structure having blocks of memory cells. Bit lines extend over the respective memory structure. In one embodiment the integrated memory assembly has what is referred to herein as a 'separate bit line architecture'. The separate bit line architecture allows the control semiconductor die to control a memory operation in parallel in the two memory semiconductor dies. Moreover, the separate bit line architecture allows for good scaling of a memory device with multiple dies bonded together.


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