The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Jun. 25, 2023
Applicant:

Seriphy Technology Corporation, Hsinchu County, TW;

Inventors:

Tzu-Wei Chiu, Hsinchu County, TW;

Chun-Wei Chang, Taipei City, TW;

Wei-Chih Chen, Taoyuan City, TW;

Che-Yen Huang, Hsinchu County, TW;

Assignee:

SERIPHY TECHNOLOGY CORPORATION, Hsinchu County, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/20 (2026.01); H10D 1/66 (2025.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01); H10W 74/00 (2026.01); H10W 80/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 20/20 (2026.01); H10D 1/665 (2025.01); H10W 70/611 (2026.01); H10W 70/65 (2026.01); H10W 74/114 (2026.01); H10W 90/00 (2026.01); H10W 90/701 (2026.01); H10W 74/00 (2026.01); H10W 80/721 (2026.01); H10W 90/297 (2026.01); H10W 90/732 (2026.01); H10W 90/794 (2026.01);
Abstract

A semiconductor structure includes a substrate, a through via penetrating the substrate, a trench capacitor, a first redistribution layer (RDL), a second RDL, and a contact feature. The trench capacitor extends from a back surface toward a front surface of the substrate, wherein the trench capacitor is separated from an active area at the front surface of the substrate. The first RDL is disposed over the front surface and electrically connecting to the through via, wherein the active area is disposed between the trench capacitor and the first RDL. The second RDL is disposed over the back surface and electrically connecting to the through via and the trench capacitor. The contact feature is disposed over the first RDL and electrically connecting to the trench capacitor through the first RDL, the through via and the second RDL. A method of manufacturing the semiconductor structure is also provided.


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