The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Aug. 10, 2023
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Chen Zhang, Santa Clara, CA (US);

Ruilong Xie, Niskayuna, NY (US);

Heng Wu, Santa Clara, CA (US);

Junli Wang, Slingerlands, NY (US);

Brent A. Anderson, Jericho, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 23/528 (2006.01); H01L 27/12 (2006.01); H01L 29/417 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H10D 30/01 (2025.01); H10D 30/63 (2025.01); H10D 64/23 (2025.01); H10D 64/68 (2025.01); H10D 86/00 (2025.01); H10D 86/01 (2025.01); H10W 10/00 (2026.01); H10W 10/17 (2026.01); H10W 20/41 (2026.01);
U.S. Cl.
CPC ...
H10D 30/63 (2025.01); H10D 30/025 (2025.01); H10D 64/258 (2025.01); H10D 64/691 (2025.01); H10D 86/01 (2025.01); H10D 86/201 (2025.01); H10W 10/014 (2026.01); H10W 10/17 (2026.01); H10W 20/427 (2026.01);
Abstract

A semiconductor device is provided. The semiconductor device includes a buried power rail, a buried oxide (BOX) layer formed on the buried power rail, a plurality of channel fins formed on the BOX layer, a bottom epitaxial layer formed on the BOX layer and between the channel fins such that the BOX layer is between the buried power rail and the bottom epitaxial layer, a gate stack formed over the bottom epitaxial layer and contacting the channel fins, the gate stack including a work function metal (WFM) layer and a high-x layer, and a top epitaxial layer formed on the gate stack. In the semiconductor device, between two adjacent ones of the channel fins the BOX layer has an opening so that the bottom epitaxial layer is electrically connected to the buried power rail.


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