The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2026
Filed:
Jun. 23, 2023
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Jinseong Heo, Suwon-si, KR;
Taehwan Moon, Suwon-si, KR;
Seunggeol Nam, Suwon-si, KR;
Hyunjae Lee, Suwon-si, KR;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 53/20 (2023.01); G11C 11/22 (2006.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01); H10B 53/30 (2023.01);
U.S. Cl.
CPC ...
H10B 53/20 (2023.02); G11C 11/223 (2013.01); H10B 51/20 (2023.02); H10B 51/30 (2023.02); H10B 53/30 (2023.02);
Abstract
A three-dimensional (3D) ferroelectric memory device may include a plurality of gate electrodes stacked on a substrate, a plurality of ferroelectric layers in contact with the plurality of gate electrodes, a plurality of intermediate electrodes in contact with the plurality of ferroelectric layers, a gate insulating layer in contact with the plurality of intermediate electrodes, and a channel layer in contact with the gate insulating layer. Widths of the intermediate electrodes may be greater than widths of the ferroelectric layers in contact with the intermediate electrodes.