The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Oct. 09, 2024
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Hari Anand Ravi, Bangalore, IN;

Phalguni Bala, Bangalore, IN;

Hajee Mohammed Shuaeb Fazeel, Bengaluru, IN;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 25/03 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03057 (2013.01); H04L 2025/03592 (2013.01);
Abstract

The present disclosure relates to a partial equalization DFE (decision feedback equalization) training method, for use with a single-ended receiver. Embodiments may include obtaining LE (lower-eye) minimum and maximum voltages for a current bit based on a preceding bit. Embodiments may also include, using the values obtained for the LE minimum and maximum voltages to compute values for an optimal LE reference voltage and an LE DFE tap-coefficient, obtaining UE (upper-eye) minimum and maximum voltages for the current bit based on the preceding bit, and using the values obtained for the UE minimum and maximum voltages to compute values for an optimal UE reference voltage and a UE DFE tap-coefficient. Embodiments may also include, using the values obtained for the LE minimum and maximum voltages, the UE minimum and maximum voltages, and the optimal LE and UE reference voltages to compute final values for the LE and UE DFE tap-coefficients.


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