The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Jul. 25, 2024
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Yu-Chung Lien, San Jose, CA (US);

Zhenming Zhou, San Jose, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/08 (2006.01); G11C 16/16 (2006.01); G11C 16/34 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3418 (2013.01); G11C 16/08 (2013.01); G11C 16/16 (2013.01); G11C 11/5635 (2013.01); G11C 16/0483 (2013.01); G11C 16/3445 (2013.01);
Abstract

In some implementations, a memory device may receive, from a host device, an erase command associated with erasing host data from a portion of a memory. The memory device may determine that the portion of the memory is associated with a reliability risk. The memory device may perform, based on determining that the portion of the memory is associated with the reliability risk, an alternative erase scheme to erase the host data from the portion of the memory, wherein during a first portion of the alternative erase scheme, a first voltage is applied to even word lines and a second voltage, that is different from the first voltage, is applied to odd word lines, and wherein during a second portion of the alternative erase scheme, a third voltage is applied to the even word lines and a fourth voltage is applied to the odd word lines.


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