The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Jun. 27, 2024
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventor:

Dung Le Tan Hoang, Hsinchu County, TW;

Assignee:

eMemory Technology Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/30 (2006.01); G11C 5/14 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01); G11C 16/26 (2006.01); H03K 3/356 (2006.01); H03K 19/00 (2006.01); H03K 19/0185 (2006.01); G05F 3/26 (2006.01);
U.S. Cl.
CPC ...
G11C 16/30 (2013.01); G11C 5/147 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); H03K 3/356113 (2013.01); H03K 19/0013 (2013.01); H03K 19/018521 (2013.01); G05F 3/262 (2013.01);
Abstract

A level shifter which includes an inverter, first/second/third/fourth N-type transistors, first/second P-type transistors and a buffer is provided. The inverter inverts an input voltage to generate an inverted input voltage based on a first reference voltage. The first N-type transistor has a gate receiving the input voltage. The second N-type transistor has a gate receiving the inverted input voltage. The third N-type transistor has a source coupled to a drain of the first N-type transistor. The fourth N-type transistor has a source coupled to a drain of the second N-type transistor. Gates of the first/second P-type transistors are coupled to the drains of the second/first N-type transistors, respectively, and sources of the first/second P-type transistors receive a second reference voltage. The level shifter generates an output voltage according to a shifted voltage on the drain terminal of the third N-type transistor or the drain terminal of the fourth N-type transistor.


Find Patent Forward Citations

Hoang, Dung Le Tan. (2026). Level shifter (U.S. Patent No. 12676196). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12676196

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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