The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Jan. 21, 2025
Applicant:

Parade Technologies, Ltd, San Jose, CA (US);

Inventors:

You Ben Yin, Hsinchu City, TW;

Quan Yu, Shanghai, CN;

Yueh-Lin Yang, Zhubei City, TW;

Assignee:

PARADE TECHNOLOGIES, LTD, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1345 (2006.01); G02F 1/1333 (2006.01); G06F 3/041 (2006.01); G06F 3/044 (2006.01);
U.S. Cl.
CPC ...
G02F 1/13452 (2013.01); G02F 1/13338 (2013.01); G02F 1/13458 (2013.01); G06F 3/0412 (2013.01); G06F 3/04166 (2019.05); G06F 3/0443 (2019.05);
Abstract

An electronic device has a display substrate including a display area, a driver area, and a fan-out area. The fan-out area is divided to a plurality of fan-out regions, and has interconnects configured to access display elements formed on the display area. The driver area is adjacent to the fan-out area and configured to receive a driver chip having a plurality of pads. The interconnects of the fan-out area include a subset of first interconnects. Each first interconnect passes a first fan-out region and a second fan-out region to access a respective display element. A first portion of the subset of first interconnects is formed on the first fan-out region with a first interconnect pitch, and a second portion of the subset of first interconnects is formed on the second fan-out region with a second interconnect pitch different from the first interconnect pitch.


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