The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2026

Filed:

Jul. 14, 2023
Applicant:

Sandisk Technologies, Inc., Milpitas, CA (US);

Inventors:

Jayavel Pachamuthu, San Jose, CA (US);

Kirubakaran Periyannan, Santa Clara, CA (US);

Daniel J. Linnen, Naperville, IL (US);

Stephen Skala, Fremont, CA (US);

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10P 74/00 (2026.01); H10D 1/68 (2025.01); H10W 42/00 (2026.01);
U.S. Cl.
CPC ...
H10P 74/277 (2026.01); H10D 1/68 (2025.01); H10W 42/00 (2026.01);
Abstract

In wafer-to-wafer bonding, a first die is bonded to a second die at a bonding interface. Various configurations of capacitors are placed along an inner portion of an edge seal of the bonded dies to detect a discontinuity in the bonding interface. These configurations include interdigitated capacitors, which can be horizontally or vertically oriented, parallel-digitated capacitors, and pillars forming a parameter around the dies with conductive portions offset from the pillar and extending inside the dies. Other configurations can be used.


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