The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2026
Filed:
May. 30, 2023
Texas Instruments Incorporated, Dallas, TX (US);
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Abstract
A microelectronic device including an integrated boot diode and a depleted mode LDMOS transistor with a charge balance layer isolated from the body region and electrically in contact with a substrate. The connection of the charge balance layer of the depleted mode LDMOS transistor directly to the substrate or ground reference eliminates body diode turn-on from the body of the transistor to the drain which typically happens above approximately 0.7 volts. In addition, the depleted mode LDMOS transistor may separate a source contact from a body contact which allows a negative bias of the body with respect to the source. Typically, the source voltage is limited to approximately 7 volts before parasitic PNP turn on becomes a factor. By negatively biasing the body with respect to the source, the maximum source voltage of the depleted mode LDMOS transistor without PNP parasitic turn-on may be increased to approximately 30 V.