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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12672338 B1

PDFFull Text
Date of Patent:
Jun. 30, 2026

Filed:

May. 25, 2023

Semiconductor device having nmos transistors and channels of pmos transistors formed of silicon/silicon germanium/silicon wherein silicon germanium not in contact with silicon oxide

Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Young Gwang Yoon, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:

IP & T GROUP LLP

Primary Examiner:

Wael M Fahmy

Assistant Examiner:

Alice W Tang

Int. Cl.
CPC ...
H10D 84/85 (2025.01); B82Y 10/00 (2011.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); B82Y 40/00 (2011.01); H10D 30/43 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0181 (2025.01); H10D 84/856 (2025.01);
Abstract

A semiconductor device includes an NMOS transistor structure formed over an NMOS area of a substrate; and a PMOS transistor structure formed over a PMOS area of the substrate. The NMOS transistor structure includes NMOS source/drain regions, and NMOS channel patterns and NMOS gate structures alternately and repeatedly stacked between the NMOS source/drain regions. The PMOS transistor structure includes PMOS source/drain regions, and PMOS channel patterns and PMOS gate structures alternately and repeatedly stacked between the PMOS source/drain regions.

Find Patent Forward Citations

Yoon, Young. (2026). Semiconductor device having nmos transistors and channels of pmos transistors formed of silicon/silicon germanium/silicon wherein silicon germanium not in contact with silicon oxide (U.S. Patent No. 12672338). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12672338

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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