The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2026

Filed:

Feb. 21, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Doohyun Lee, Suwon-si, KR;

Heonjong Shin, Suwon-si, KR;

Seon-Bae Kim, Suwon-si, KR;

Jaeran Jang, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/69 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 30/701 (2025.01); H10D 62/151 (2025.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01);
Abstract

In some embodiments, the semiconductor device includes a substrate comprising a cell region, a dummy region spaced apart from the cell region in a first direction, and a border region between the cell region and the dummy region, an active pattern on the cell region, a device isolation layer on the substrate, source/drain patterns on the active pattern and channel patterns between the source/drain patterns, cell gate electrodes crossing the channel patterns in a second direction, active contacts disposed on the cell region and between the cell gate electrodes and coupled to the source/drain patterns, dummy gate electrodes on the dummy region and on the device isolation layer, dummy contacts on the dummy region and on a side surface of each of the dummy gate electrodes, an interlayer insulating layer on the side surface of each of the dummy gate electrodes, and a dam structure on the border region.


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