The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2026

Filed:

Dec. 26, 2023
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Ting-Yu Chang, Zhubei City, TW;

Jian-Hsing Lee, Hsinchu City, TW;

Yeh-Ning Jou, Hsinchu City, TW;

Chieh-Yao Chuang, Kaohsiung City, TW;

Hsien-Feng Liao, Taichung City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H10D 30/60 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10D 30/60 (2025.01); H10D 62/116 (2025.01); H10D 62/124 (2025.01);
Abstract

An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes an N-type deep well region (DNW), first and second high-voltage P- and N-type well regions (first and second HVPW and HVNW), a low-voltage N-type well region (LVNW), first and second P- and first N-type doped regions in a P-type semiconductor substrate, and a gate structure. The first and second HVPW and HVNW are located on the DNW. The LVNW is located on the first HVPW. The first P- and N-type doped regions and second P-type doped region are located on the LVNW and the second HVNW and HVPW. The first P-type doped region is electrically connected to a first voltage source. The gate structure on the first and second HVPW and the first HVNW, the second P-type doped region and the first N-type doped region are electrically connected to a second voltage source.


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