The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2026
Filed:
Aug. 06, 2024
Cadence Design Systems, Inc., San Jose, CA (US);
Anirudha Anil Shelke, Pune, IN;
Avinash Ugrappa, Bengaluru, IN;
Ashwin S. M., Kerala, IN;
Venkata Mahesa Thorata, Toronto, CA;
Mahabaleshwara Maha, Benagalura Karnataka, IN;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Technologies for optimizing multi-tap Decision Feedback Equalizer (DFE) training in the memory physical (PHY) layer may be described. A receiver circuit includes analog and digital circuitry. The analog circuitry includes a single de-serializer and a set of DFE taps. The digital circuitry includes a register to store a copy of a set of training patterns. The digital circuitry performs byte alignment using a first training pattern. The digital circuitry may match error bits received from the single de-serializer with data bits of the copy of the set of training patterns. The digital circuitry may calibrate the set of DFE taps using the error bits and the data bits.