The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2026

Filed:

Dec. 14, 2023
Applicant:

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Enea Dimroci, Borgo San Dalmazzo, IT;

Roberta Priolo, Milan, IT;

Francesco Battini, Milan, IT;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 30/32 (2020.01); G01R 31/317 (2006.01); G01R 31/3185 (2006.01); G06F 11/27 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318536 (2013.01); G01R 31/31725 (2013.01); G01R 31/318525 (2013.01); G01R 31/318544 (2013.01); G06F 11/27 (2013.01); G06F 30/32 (2020.01);
Abstract

According to an embodiment, a test system for serially testing of finite state machine circuits using scan chains is proposed. Each scan chain is coupled to a finite state machine circuit to test the finite state machine circuit coupled thereto. Each scan chain has a number of input terminals and one output terminal. The test system includes a dispatcher input interface with a number of input terminals and multiple sets of output terminals, where each set of output terminals includes multiple output terminals coupled to the input terminals of an associated scan chain. The test system further includes a dispatcher output interface with multiple input terminals and one output terminal. The output terminal of each scan chain is coupled to one of the input terminals of the dispatcher output interface.


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