The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Nov. 08, 2022
Applicant:

Unimicron Technology Corp., Taoyuan, TW;

Inventors:

Yu-Shen Chen, Taoyuan, TW;

I-Ta Tsai, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 74/01 (2026.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 70/652 (2026.01); H10W 70/655 (2026.01); H10W 70/685 (2026.01); H10W 72/00 (2026.01); H10W 72/90 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01); H10W 90/10 (2026.01);
U.S. Cl.
CPC ...
H10W 74/019 (2026.01); H10W 70/05 (2026.01); H10W 70/685 (2026.01); H10W 74/114 (2026.01); H10W 90/00 (2026.01); H10W 70/093 (2026.01); H10W 70/60 (2026.01); H10W 70/6528 (2026.01); H10W 70/655 (2026.01); H10W 72/823 (2026.01); H10W 72/932 (2026.01); H10W 72/9445 (2026.01); H10W 90/10 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01);
Abstract

The present disclosure provides a circuit board with an embedded chip, which includes a dielectric layer, a first circuit layer, a chip, a conductive connector, and an insulating protection layer. The first circuit layer includes at least one first trace in the dielectric layer. The chip is in the dielectric layer and adjacent to the first trace, where the chip includes a plurality of chip pads at an upper surface of the chip. The conductive connector is on the upper surface of the chip and on the first circuit layer, where a lower surface of the conductive connector contacts at least one chip pad of the chip pads and an upper surface of the first trace. The insulating protection layer is on the chip, the first circuit layer, and the conductive connector, where the insulating protection layer contacts the upper surface of the chip.


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