The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Apr. 04, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Young Lyong Kim, Anyang-si, KR;

Hyunsoo Chung, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 70/685 (2026.01); H10W 70/60 (2026.01); H10W 72/90 (2026.01); H10W 74/10 (2026.01); H10W 80/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/685 (2026.01); H10W 74/111 (2026.01); H10W 90/00 (2026.01); H10W 70/60 (2026.01); H10W 72/9445 (2026.01); H10W 80/743 (2026.01); H10W 90/724 (2026.01);
Abstract

A semiconductor package includes a first semiconductor chip on a package substrate, a second semiconductor chip on the first semiconductor chip and having a redistribution layer on a bottom surface thereof, under-bump pads on a bottom surface of the redistribution layer, first solders adjacent to the first semiconductor chip and connecting first pads of the under-bump pads to substrate pads of the package substrate, and a molding layer on the package substrate and covering the first and second semiconductor chips and the first solders. Second pads of the under-bump pads are in direct contact with a top surface of the first semiconductor chip. The first pads are connected through the redistribution layer to an integrated circuit of the second semiconductor chip. The second pads are insulated from the integrated circuit of the second semiconductor chip.


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