The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Aug. 19, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kunal R. Parekh, Boise, ID (US);

Bret K. Street, Meridian, ID (US);

Terrence B. Mcdaniel, Boise, ID (US);

Jaekyu Song, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 70/68 (2026.01); H10W 70/60 (2026.01); H10W 70/62 (2026.01); H10W 70/65 (2026.01); H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 74/00 (2026.01); H10W 74/15 (2026.01);
U.S. Cl.
CPC ...
H10W 70/68 (2026.01); H10W 70/611 (2026.01); H10W 70/641 (2026.01); H10W 70/65 (2026.01); H10W 90/00 (2026.01); H10W 90/401 (2026.01); H10W 90/701 (2026.01); H10W 70/60 (2026.01); H10W 70/682 (2026.01); H10W 72/877 (2026.01); H10W 74/00 (2026.01); H10W 74/15 (2026.01); H10W 90/724 (2026.01); H10W 90/732 (2026.01); H10W 90/734 (2026.01);
Abstract

A semiconductor device assembly comprises a package substrate including (i) an upper surface having a plurality of internal contacts, (ii) a lower surface having a plurality of external contacts coupled to the plurality of internal contacts, and (iii) a cavity extending into the package substrate. The assembly further comprises a stack of first semiconductor devices disposed in the cavity, an uppermost first semiconductor device of the stack having a plurality of stack contacts, and an interposer including (i) a bottom surface having a first plurality of lower contacts coupled to the plurality of stack contacts and a second plurality of lower contacts coupled to the plurality of internal contacts, and (ii) a top surface having a plurality of upper contacts coupled to the first and second pluralities of lower contacts. The assembly further comprises a second semiconductor device including a plurality of die contacts coupled to the plurality of upper contacts.


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