The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Nov. 14, 2023
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Tek PO Rinus Lee, Albany, NY (US);

Gyanaranjan Pattanaik, Albany, NY (US);

Kenichi Imakita, Albany, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/00 (2026.01); H10W 20/41 (2026.01); H10W 20/42 (2026.01);
U.S. Cl.
CPC ...
H10W 20/042 (2026.01); H10W 20/037 (2026.01); H10W 20/045 (2026.01); H10W 20/063 (2026.01); H10W 20/425 (2026.01); H10W 20/42 (2026.01);
Abstract

A method of processing a substrate includes forming an amorphous silicon (a-Si) layer over the substrate, where the substrate includes a dielectric layer and a conductive layer, and the a-Si liner covers a surface of the dielectric layer and a surface of the conductive layer. The method includes converting the a-Si liner into a silicon-containing layer including a metal; and depositing the metal over the silicon-containing layer using the silicon-containing layer as a seed layer for the depositing, where the metal deposited over the silicon-containing layer and the conductive layer are electrically connected.


Find Patent Forward Citations

Lee, Tek PO Rinus. (2026). Low resistance liner (U.S. Patent No. 12666933). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12666933

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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