The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2026
Filed:
Jun. 16, 2022
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Shih-Chang Wang, Tainan City, TW;
Hsiu-Hui Huang, Hsinchu City, TW;
Feng-Ju Chang, Hsinchu City, TW;
Yen-Fong Chan, Hsinchu County, TW;
Chien-Huei Chen, Kaohsiung City, TW;
Xiaomeng Chen, Hsinchu County, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;
Abstract
A system configured to detect defects on a wafer is provided. The system includes an inspection subsystem configured to acquire scan data of a target region on the wafer. The target region comprises a plurality of circuit layout streaming data on the wafer and the defects in proximity to the circuit layout streaming data or in the circuit layout streaming data. A graphic design subsystem (GDS) is configured to store a map of circuit layout streaming data of the wafer. A software tool for designing electronic systems is configured to label the scan data with attributes from the map of circuit layout streaming data. A decision subsystem is configured to qualify the process based on a predetermined defect level from the labeled scan data by using a multi-dimension clustering method, wherein the predetermined defect level is an accumulated defect formed on the semiconductor wafer during processing.