The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Jul. 06, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Wan Chen Hsieh, Hsinchu City, TW;

Zhen-Cheng Wu, Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01); H10P 14/60 (2026.01);
U.S. Cl.
CPC ...
H10D 62/121 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 64/017 (2025.01); H10D 84/0144 (2025.01); H10D 84/038 (2025.01); H10P 14/6336 (2026.01);
Abstract

A method includes the following steps. A transistor including a first gate structure is formed on a first substrate. A first dielectric layer is deposited over the transistor using plasma enhanced atomic layer deposition (PEALD). A multilayer stack is formed on a second substrate. The multilayer stack comprises alternately stacked semiconductor layers and sacrificial layers. A second dielectric layer is deposited over the multilayer stack using a plasma enhanced atomic layer deposition (PEALD). The second dielectric layer is bonded with the first dielectric layer. The sacrificial layers are replaced with a second gate structure.


Find Patent Forward Citations

Loading…